Field Programmable Gate Array Implementation Research Articles

Dynamic Analysis and Field-Programmable Gate Array Implementation of a 5D Fractional-Order Memristive Hyperchaotic System with Multiple Coexisting Attractors

On the basis of the chaotic system proposed by Wang et al. in 2023, this paper constructs a 5D fractional-order memristive hyperchaotic system (FOMHS) with multiple coexisting attractors through coupling of magnetic control memristors and dimension expansion. Firstly, the divergence, Kaplan–Yorke dimension, and equilibrium stability of the chaotic model are studied. Subsequently, we explore the construction of the 5D FOMHS, introducing the definitions of the Caputo differential operator and the Riemann–Liouville integral operator and employing the Adomian resolving approach to decompose the linears, the nonlinears, and the constants of the system. The complex dynamic characteristics of the system are analyzed by phase diagrams, Lyapunov exponent spectra, time-domain diagrams, etc. Finally, the hardware circuit of the proposed 5D FOMHS is performed by FPGA, and its randomness is verified using the NIST tool.

AEKA: FPGA Implementation of Area-Efficient Karatsuba Accelerator for Ring-Binary-LWE-Based Lightweight PQC

Lightweight PQC-related research and development have gradually gained attention from the research community recently. Ring-Binary-Learning-with-Errors (RBLWE)-based encryption scheme (RBLWE-ENC), a promising lightweight PQC based on small parameter sets to fit related applications (but not in favor of deploying popular fast algorithms like number theoretic transform). To solve this problem, in this article, we present a novel implementation of hardware acceleration for RBLWE-ENC based on Karatsuba algorithm, particularly on the field-programmable gate array (FPGA) platform. In detail, we have proposed an area-efficient Karatsuba Accelerator (AEKA) for RBLWE-ENC, based on three layers of innovative efforts. First of all, we reformulate the signal processing sequence within the major arithmetic component of the KA-based polynomial multiplication for RBLWE-ENC to obtain a new algorithm. Then, we have designed the proposed algorithm into a new hardware accelerator with several novel algorithm-to-architecture mapping techniques. Finally, we have conducted thorough complexity analysis and comparison to demonstrate the efficiency of the proposed accelerator, e.g., it involves 62.5% higher throughput and 60.2% less area-delay product (ADP) than the state-of-the-art design for n =512 (Virtex-7 device, similar setup). The proposed AEKA design strategy is highly efficient on the FPGA devices, i.e., small resource usage with superior timing, which can be integrated with other necessary systems for lightweight-oriented high-performance applications (e.g., servers). The outcome of this work is also expected to generate impacts for lightweight PQC advancement.

Adaptive radar pulse detection design based on difference of box filter

AbstractPrecise radar pulse detection is the premise of electronic support measures. A constant false alarm rate (CFAR) detection algorithm based on difference of box (DOB) filter is proposed to realise low‐complexity and environment‐adaptive radar pulse detection, and the principle behind the proposed algorithm is revealed. Specifically, the DOB filter is adopted to extract the rising edges and falling edges of radar pulses, and the signal variation law of probability density functions (PDFs) during the process of DOB filter are first theoretically analysed. Based on the derived PDFs, dynamic detection threshold and fixed threshold factor for the proposed CFAR algorithm based on DOB filter are deduced to detect the presence of radar pulses. Furthermore, the closed‐form expression of the detection probability is derived. Simulations and on‐board field programmable gate arrays implementation verify the superiority of the proposed CFAR algorithm based on DOB filter. Simulation results show that the proposed algorithm performs well in detecting various types of pulse signals, the detection probability ≥99% on condition that the signal‐to‐noise ratio ≥3 dB and false alarm probability = 10−8. Moreover, the proposed CFAR algorithm based on DOB filter can deal with both singular pulses and pulse on pulse signals.

Securing IoT devices with fast and energy efficient implementation of PRIDE and PRESENT ciphers

The rise of low-power, cost-efficient internet-connected devices has led to a need for lightweight cryptography. The lightweight block cipher PRIDE, designed by Martin R. Albrecht, is one of the most efficient ciphers designed for IoT-constrained environments. It is useful for connected devices, requires fewer resources to implement, and has high performance. PRIDE is a software-oriented lightweight cipher optimized for microcontrollers. This paper focuses on the FPGA implementation of the PRIDE cipher by keeping throughput, energy, and power consumption metrics focused. The paper also presents a novel and simpler diagrammatical view of a Matrix Layer implementation of the PRIDE cipher. We also implemented the PRESENT cipher using the same metrics. We analyzed different design metrics on Field Programmable Gate Arrays (FPGAs) and compared the metrics of the PRIDE implementation with the well-known cipher PRESENT. This gives us an insight into the efficiency and reliability of PRIDE in IoT-constrained environments. We also proposed different architectures of the PRIDE cipher for 16-bit and 32-bit datapaths.

Voltage Scaled Low Power DNN Accelerator Design on Reconfigurable Platform

The exponential emergence of Field-Programmable Gate Arrays (FPGAs) has accelerated research on hardware implementation of Deep Neural Networks (DNNs). Among all DNN processors, domain-specific architectures such as Google’s Tensor Processor Unit (TPU) have outperformed conventional GPUs (Graphics Processing Units) and CPUs (Central Processing Units). However, implementing low-power TPUs in reconfigurable hardware remains a challenge in this field. Voltage scaling, a popular approach for energy savings, can be challenging in FPGAs, as it may lead to timing failures if not implemented appropriately. This work presents an ultra-low-power FPGA implementation of a TPU for edge applications. We divide the systolic array of a TPU into different FPGA partitions based on the minimum slack value of different design paths of Multiplier Accumulators (MACs). Each partition uses different near-threshold (NTC) biasing voltages to run its FPGA cores. The biasing voltage for each partition is roughly calculated by the proposed static schemes. However, further calibration of biasing voltage is performed by the proposed runtime scheme. To overcome the timing failure caused by NTC, the MACs with higher minimum slack are placed in lower-voltage partitions, while the MACs with lower minimum slack paths are placed in higher-voltage partitions. The proposed architecture is implemented in a commercial platform, namely Vivado with Xilinx Artix-7 FPGA and academic platform VTR with 22 nm, 45 nm and 130 nm FPGAs. Any timing error caused by NTC can be caught by the Razor flipflop used in each MAC. The proposed voltage-scaled, partitioned systolic array can save 3.1% to 11.6% of dynamic power in Vivado and VTR tools, respectively, depending on the FPGA technology, partition size, number of partitions and biasing voltages. The normalized performance and accuracy of benchmark models running on our low-power TPU are very competitive compared to existing literature.

Optimizing FPGA implementation of high-precision chaotic systems for improved performance.

Developing chaotic systems-on-a-chip is gaining much attention due to its great potential in securing communication, encrypting data, generating random numbers, and more. The digital implementation of chaotic systems strives to achieve high performance in terms of time, speed, complexity, and precision. In this paper, the focus is on developing high-speed Field Programmable Gate Array (FPGA) cores for chaotic systems, exemplified by the Lorenz system. The developed cores correspond to numerical integration techniques that can extend to the equations of the sixth order and at high precision. The investigation comprises a thorough analysis and evaluation of the developed cores according to the algorithm complexity and the achieved precision, hardware area, throughput, power consumption, and maximum operational frequency. Validations are done through simulations and careful comparisons with outstanding closely related work from the recent literature. The results affirm the successful creation of highly efficient sixth-order Lorenz discretizations, achieving a high throughput of 3.39 Gbps with a precision of 16 bits. Additionally, an outstanding throughput of 21.17 Gbps was achieved for the first-order implementation coupled with a high precision of 64 bits. These outcomes set our work as a benchmark for high-performance characteristics, surpassing similar investigations reported in the literature.

FPGA implementation of DTCWT architecture's high-speed DA structure for OFDM-based transceiver with CS

Communication systems at millimeter-wave (mm-wave) frequencies with high propagation losses use radio frequency (RF) budget analysis. RF system gains and losses ensure the receiver can recover the broadcast signal. Modern communication systems use compressive sensing (CS) and discrete wavelet transform (DWT). Hardware implementation is hard. Fieldprogrammable gate arrays (FPGA) adaptability, configurability, and processing speed make them popular. More mm-wave transceivers use FPGAs and advanced signal processing. FPGA-based mm-wave transceivers use compressed sensing and dual-tree complex wavelet transform (DTCWT). RF budget analysis recovers receiver signals. Energy and data efficiency transceivers have baseband processors, transmitters, and receivers. RF-to-mm-wave transmitter. Receiver demodulation and baseband conversion. CS and DTCWT processing modules boost baseband signal processing 5 Gbps Xilinx virtex-6 FPGAs. The system retrieves the signal while conserving power, according to simulations and testing. This study found that FPGA-based mm-wave transceivers can use advanced signal processing in future high-speed communication systems.

Investigation on Vision System: Digital FPGA Implementation in Case of Retina Rod Cells.

The development of prostheses and treatments for illnesses and recovery has recently been centered on hardware modeling for various delicate biological components, including the nervous system, brain, eyes, and heart. The retina, being the thinnest and deepest layer of the eye, is of particular interest. In this study, we employ the Nyquist-Based Approximation of Retina Rod Cell (NBAoRRC) approach, which has been adapted to utilize Look-Up Tables (LUTs) rather than original functions, to implement rod cells in the retina using cost-effective hardware. In modern mathematical models, numerous nonlinear functions are used to represent the activity of these cells. However, these nonlinear functions would require a substantial amount of hardware for direct implementation and may not meet the required speed constraints. The proposed method eliminates the need for multiplication functions and utilizes a fast, cost-effective rod cell device. Simulation results demonstrate the extent to which the proposed model aligns with the behavior of the primary rod cell model, particularly in terms of dynamic behavior. Based on the results of hardware implementation using the Field-Programmable Gate Arrays (FPGA) board Virtex-5, the proposed model is shown to be reliable, consume 30 percent less power than the primary model, and have reduced hardware resource requirements. Based on the results of hardware implementation using the reconfigurable FPGA board Virtex-5, the proposed model is reliable, uses 30% less power consumption than the primary model in the worth state of the set of approximation method, and has a reduced hardware resource requirement. In fact, using the proposed model, this reduction in the power consumption can be achieved. Finally, in this article, by using the LUT which is systematically sampled (Nyquist rate), we were able to remove all costly operators in terms of hardware (digital) realization and achieve very good results in the field of digital implementation in two scales of network and single neuron.

Flare: An FPGA-Based Full Precision Low Power CNN Accelerator with Reconfigurable Structure.

Convolutional neural networks (CNNs) have significantly advanced various fields; however, their computational demands and power consumption have escalated, posing challenges for deployment in low-power scenarios. To address this issue and facilitate the application of CNNs in power constrained environments, the development of dedicated CNN accelerators is crucial. Prior research has predominantly concentrated on developing low precision CNN accelerators using code generated from high-level synthesis (HLS) tools. Unfortunately, these approaches often fail to efficiently utilize the computational resources of field-programmable gate arrays (FPGAs) and do not extend well to full precision scenarios. To overcome these limitations, we integrate vector dot products to unify the convolution and fully connected layers. By treating the row vector of input feature maps as the fundamental processing unit, we balance processing latency and resource consumption while eliminating data rearrangement time. Furthermore, an accurate design space exploration (DSE) model is established to identify the optimal design points for each CNN layer, and dynamic partial reconfiguration is employed to maximize each layer's access to computational resources. Our approach is validated through the implementation of AlexNet and VGG16 on 7A100T and ZU15EG platforms, respectively. We achieve an average convolutional layer throughput of 28.985 GOP/s and 246.711 GOP/s for full precision. Notably, the proposed accelerator demonstrates remarkable power efficiency, with a maximum improvement of 23.989 and 15.376 times compared to current state-of-the-art FPGA implementations.

The Design of FIR Filter Based on improved DA Algorithm and its FPGA implementation: REVIEW

The Design of FIR Filter Based on improved DA Algorithm and its FPGA implementation: REVIEW

FPGA acceleration of convolutional neural networks: Current applications and future prospects

In the contemporary era of big data, the utilization of deep learning technology has become widespread in the extraction of valuable analytical insights from the data under consideration. This technology finds extensive applications in various domains, including image information recognition, speech processing, and text language analysis. When it comes to accelerating convolutional neural networks (CNNs), the utilization of Field-Programmable Gate Arrays (FPGAs) offers distinct advantages over other hardware accelerators. Nevertheless, it is important to acknowledge that FPGA-based acceleration also comes with its own structural limitations. This article places its focus on two main aspects: firstly, it delves into the present-day application landscape and the latest developmental trajectories of convolutional neural networks. Secondly, it elucidates the inherent characteristics of FPGA implementations of CNNs. Furthermore, the article conducts a comprehensive examination of the pertinent constraints associated with FPGA-accelerated deep learning algorithms. The discussion extends beyond the present moment and ventures into the future, offering insights into the potential advancements in the field of deep learning. Importantly, it also brings into focus the prospective avenues for further research regarding the application of FPGAs in the domain of convolutional neural networks.

New High-Rate Timestamp Management with Real-Time Configurable Virtual Delay and Dead Time for FPGA-Based Time-to-Digital Converters

Modern applications require the ability to measure time events with high resolution, a full-scale range, and multiple input channels. Time-to-Digital Converters (TDCs) are a popular option to convert time intervals into timestamps. To reduce the time-to-market and Non-Recurring Engineering (NRE) costs, a Field-Programmable Gate Array (FPGA) implementation has been chosen. The high number of requested bits and channels, however, gives rise to routing congestion issues when routed in a parallel manner. In this paper, we will propose and analyze a novel solution, the Belt-Bus (BB), which involves a parallel-to-serial conversion of the timestamp stream coming from the TDC while maintaining chronological order and a sufficient high rate, and flagging the presence of timestamp overflow. Moreover, two new useful features are added. The first is a “Virtual Delay” to compensate for offsets due to cable length and FPGA routing path mismatch. The second is a “Virtual Dead-Time” to filter out unforeseen events. Finally, the BB was tested on a Xilinx 28 nm 7-Series Kintex-7 325T FPGA, achieving an overall data rate of 199.9 Msps with very limited resource usage (i.e., lower than a total of 4.5%), consuming only 480 mW in a 16-channel implementation.

RF direct sampling and processing electronics for SHINE cavity BPM system

Cavity BPMs are crucial for achieving submicron beam alignment in X-ray Free-Electron Lasers (XFEL), particularly in undulator sections. These monitors typically generate RF signals in the S, C, or X band regions. Due to the limitations of analog-to-digital converter's (ADC) bandwidth and sampling rates, and digital signal processing capabilities, heterodyne and homodyne receivers are often employed to down-convert the RF signal to an intermediate frequency (IF) or baseband (Zero IF) respectively before digital sampling. The digitized signal is then processed by Field Programmable Gate Array (FPGA) to get the beam position and phase information. An RF direct-sampling beam signal processor has been developed using ADCs with a bandwidth of 9 GHz and a sampling rate of 2.6 GSPS, and a powerful system-on-chip FPGA. In addition, a prototype RF module without complex down conversion devices has been designed for the SHINE (Shanghai High Repetition Rate XFEL and Extreme Light Facility) cavity BPM. The processor and the RF module make a novel RF direct sampling and processing cavity BPM electronics for SHINE. This is the first attempt to use direct sampling electronics in the C band cavity BPM system. The analog signal processing chain is greatly simplified compared to the down-conversion structure. The performance of this electronics has been analyzed and evaluated in laboratory. The amplitude relative error is 2.0 × 10-4, surpassing the required accuracy of 1 × 10-3 for cavity BPM systems. The phase error is 14 femtoseconds (fs), which also meets the requirements for an RF Beam Arrival Time Monitor (BAM) system. Additionally, the paper introduces the cavity BPM signal processing algorithms and their implementation in FPGA. The processor can deliver pulse-to-pulse beam position measurement above 1 MHz. The RF direct-sampling electronics represents significant advancements in cavity BPM system, large-scale application can be carried out in accelerator facilities like SHINE.

Enhancing Embedded Object Tracking: A Hardware Acceleration Approach for Real-Time Predictability.

While Siamese object tracking has witnessed significant advancements, its hard real-time behaviour on embedded devices remains inadequately addressed. In many application cases, an embedded implementation should not only have a minimal execution latency, but this latency should ideally also have zero variance, i.e., be predictable. This study aims to address this issue by meticulously analysing real-time predictability across different components of a deep-learning-based video object tracking system. Our detailed experiments not only indicate the superiority of Field-Programmable Gate Array (FPGA) implementations in terms of hard real-time behaviour but also unveil important time predictability bottlenecks. We introduce dedicated hardware accelerators for key processes, focusing on depth-wise cross-correlation and padding operations, utilizing high-level synthesis (HLS). Implemented on a KV260 board, our enhanced tracker exhibits not only a speed up, with a factor of 6.6, in mean execution time but also significant improvements in hard real-time predictability by yielding 11 times less latency variation as compared to our baseline. A subsequent analysis of power consumption reveals our approach's contribution to enhanced power efficiency. These advancements underscore the crucial role of hardware acceleration in realizing time-predictable object tracking on embedded systems, setting new standards for future hardware-software co-design endeavours in this domain.

The Data Compression Method and FPGA Implementation in the Mars Rover Subsurface-Penetrating Radar on the Tianwen-1 Mission

Since Mars is far away from Earth, the propagation delay between Mars and Earth is very large. To ensure the effective use of the link transmission bandwidth, China’s first Mars exploration mission has put forward a demand for data compression for all scientific payloads. The on-board mature algorithms for data compression are mainly focused on optical images and microwave imaging radar applications. No articles have been published on data compression methods that are applied to subsurface-penetrating radar. Based on the background of this application, this paper proposes a logarithmic lossy compression algorithm which can meet the mission requirements for high compression ratios of 4:1 and 2.5:1. Its compression error is less than that of the block adaptive quantization (BAQ) algorithm. The algorithm is not only easy to implement on field-programmable gate array (FPGA) platforms, but also offers simple ground decompression and fast imaging. The experimental results show that high compression ratios of 4:1 and 2.5:1 can be realized, even if the data in and between traces do not have a strong correlation. And its relative error is less than 2%, which is a new type of high-efficiency data compression method that can be implemented on-board to meet with the demand of subsurface penetrating radar.

Bistability and chaotic behaviors in a 4D cancer oncolytic Virotherapy mathematical model: Pspice and FPGA implementations

Oncolytic viruses (OVs) exploit characteristics of mass cells and tumor-related reaction of the body to the presence of antigen, to lyse malignant cells and modulate the tumor microenvironment. However, the effective clinical utilization of these powerful treatment modules necessitates their logical control, especially in order to prevent solid and metastatic outgrowths. Hence, it is imperative to develop methods to protect a virus from the annihilating surroundings from the bloodstream when traveling to tumor locations. Our article reports on bistability and chaotic behavior in a 4D cancer virotherapy model. We find that unstable, stable and chaotic behaviors can appear in the model when tuning some of its parameters. With the help of the chart of dynamic behaviors in parameter spaces, numerical investigations of the system’s characteristics are analyzed followed by a discussion of the obtained results. It appears that the local transition change from an invariant one-torus (IT1) to its two-torus (IT2) counterpart can be found in the system and this undergoes a Neimark-Saker (NS) change of direction. As the increasing rate of immune effector enhance, the immune cells amount increases and as a consequence, the virotherapy dynamics becomes chaotic with a pronounced Lyapunov exponent. This can result to the failure of the virotherapy due to the interference of the immune cells with viruses. We also focus our study on the deign of ad-hoc electronic and Field Programmable Gate Arrays (FPGA) implementations of the cancer virotherapy’s model, to illustrate the obtained results.

Adaptive wavelet transform defogging scheme for real-time video restoration with field programmable gate array implementation

Adaptive wavelet transform defogging scheme for real-time video restoration with field programmable gate array implementation

An improved CFAR algorithm for multiple environmental conditions

AbstractThe primary objective of radar digital signal processing is to detect and identify targets in complicated situations, such as those involving clutter or several closely positioned targets. The constant false alarm rate (CFAR) method is more effective for target recognition and has better control over the false alarm rate. Many studies have been conducted on the design of CFAR, but previous CFAR algorithms have not been effective in all or most environmental fields and target scenarios. In this study, an algorithm called Censored Mean Clutter Map CFAR (CM-CM CFAR) has been developed and tested for various environmental conditions. When compared to a fixed false alarm rate, the suggested CFAR algorithm’s Monte Carlo simulation results demonstrated a high detection probability in a variety of environments. This work designs a real-time CM-CM CFAR processor using field-programmable gate array (FPGA) technologies. Xilinx ARTIX 7 FPGA technology is used to develop and map a scalable parallel framework. Consequently, the implementation required 23,741 LUTs and 1825 FF. It is verified that the complexity and operating speed of the suggested CFAR processor are extremely appropriate for real-time implementation when compared to the results of the previously proposed FPGA implementation.

Designing hardware for a robust high-speed cryptographic key generator based on multiple chaotic systems and its FPGA implementation for real-time video encryption

AbstractRecent advancements in communication technologies have highlighted the pivotal role of information security for all individuals and entities. In response, researchers are increasingly focusing on cryptographic solutions to ensure the reliability of confidential information. Recognizing the superiority of chaotic systems preference as entropy source of cryptographic systems, this paper proposes a novel true random number generator (TRNG) design by combining four different chaotic systems outputs, tailored for real-time video encryption application. These chaotic systems are continuous-time Lorenz and fractional-order Chen-Lee systems, as well as discrete-time Logistic and Tent maps. This study generates true random bit (TRB) sequences at a high bit rate (25 Mbps) through the hardware implementations of four distinct chaotic systems to have the best statistical randomness in the resulting output. Then, the cryptographic true random key bits (8-bit at 25 MHz frequency) are employed in the post-processing with real-time video data by using the XOR operation, a fundamental post-processing algorithm. The real-time video encryption application is executed on an experimental assembly, composed of a Field Programmable Gate Array (FPGA) development kit, an OV7670 camera module, a VGA monitor, and prototype circuit boards for the chaotic systems. To evaluate the effectiveness of the proposed encryption system, several security assessments are conducted. These include NIST SP 800 − 22 statistical tests, FIPS 140-1 standards, chi-square tests, histogram and correlation analysis, and NPCR and UACI differential attack resilience tests. Consequently, the findings suggest that the presented real-time embedded cryptosystem is robust and suitable for secure communications, particularly in the realm of video transmission.

Dynamic analysis and FPGA implementation of a 5D multi-wing fractional-order memristive chaotic system with hidden attractors

In this paper, inspired by a 3D multi-wing chaotic system proposed by Sahoo et al. in 2022, we presented a 5D multi-wing fractional-order memristive chaotic system with hidden attractors by increasing dimensionality and introducing memristor. Firstly, the equilibrium point of the 5D fractional-order memristive chaotic system was analyzed, and it was found that it has hidden attractors. The adomian decomposition algorithm was used to decompose the nonlinear term of the system. Then, the dynamic behavior of the system was analyzed using phase diagrams, Lyapunov exponent spectrums, and bifurcation diagrams. The hardware circuit of the 5D multi-wing fractional-order chaotic system was implemented using a field programmable gate array (FPGA) and experimentally verified. The experimental results are consistent with the numerical simulation results in MATLAB. Finally, the good randomness of the system was verified through NIST testing.